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ASIC设计主管工程师 |
2007-3-30
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某知名半导体公司上海研究中心
任职要求：
1、电子工程相关专业硕士以上，3－5年以上工作经验( Master, or above in EE/Computer , 5~ years)
2、精通Verilog/VHDL编程(Strong capiblity of Verilog/VHDL coding. )
3、有CPU/MCU开发经验，熟悉8/16/32位CPU/MCU(8051或ARM)架构和开发调试系统。(Familiarity with processor architecture ( 8051orARM) , experience of 8/16/32 CPU/MCU developement and debugging system.)
4、熟悉主流的EDA设计工具和流程，例如Cadence，Synopsys等( Familiarity with at least one major ASIC EDA tool from Cadence, Synopsys)
5、有FPGA设计和调试经验者优先(FPGA design/debugging experience will be a big plus)
6、具备良好的交流能力和团队协作精神( Good communication and interpersonal skill. Self-motivated team player in the SOC design environment. )
职位描述：
1、嵌入式CPU内核/MCU及平台IP的开发.(To perform Embedded CPU/MCU and CPU Platfom Auxiliary IPs Design.)
2、嵌入式CPU内核/MCU及平台IP的验证(Build Verification Environment for embedded CPU/MCU cores and CPU Platform Auxiliary IPS.)
3、嵌入式CPU内核/MCU及平台IP的ASIC应用支持.(Support the AISC application to embedded CPU/MCU cores and CPU Platform Auxiliary IPs )
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